This disclosure relates generally to the design, implementation and utilization of electronic circuits, and more specifically, to a recoverable and reconfigurable pipeline structure for use in electronic circuits.
Electronic circuits (e.g., integrated circuits (ICs), microprocessors, microcontrollers, digital signal processors, digital signal controllers, sensors, RF power ICs, power management ICs, system on a chip (SoC) devices, and the like) have become ubiquitous in recent years. While the number of electronic circuits has steadily increased, there has been a concomitant decrease in the average size of such electronic circuits and the discrete devices used in their construction. So-called ‘transistor scaling’ has increased transistor density resulting in decreased device size and active logic power consumption in modern integrated circuits of all types.
Adherence to Moore's law in modern integrated circuit fabrication does however create a number of negative consequences or limitations. Increasing transistor density similarly increases the likelihood of fabrication errors or electromagnetic compatibility issues (e.g., capacitive or inductive coupling) while decreasing area available for scan, built in self-test (BIST), and other testing and verification components and vastly increases the place and route complexity of electronic circuits. Another significant issue, particularly with regard to modern battery-powered electronic devices, is leakage-current and associated power dissipation of inactive logic within electronic circuits. Leakage current can include reverse-biased junction leakage current, gate-induced drain leakage, gate direct-tunneling leakage and subthreshold or “weak inversion” leakage.
In conventional electronic circuits, a number of techniques have been adopted to address some of the described issues stemming from transistor scaling. The majority of these techniques rely on either a reduction (scaling) or a removal (gating) of signals such as clock signals and power supply rail voltages that are applied to functional elements or portions thereof of electronic circuits. While such techniques reduce power consumption of inactive elements, they typically require that the state of the associated electronic circuit be saved either locally in specialized state-retention storage elements whose storage capabilities are not impacted by scaling or gating or remotely (e.g., in system memory or backing store). Remote storage of system state requires that storage resource contention and remote storage latency be addressed and is therefore undesirable. Local, state-retention storage element state storage is typically simpler and faster to implement but consumes more die area, increases leakage power dissipation, negatively impacts electronic circuit performance, and increases design complexity in order to routing the separate power supply rails typically required by such storage elements, counteracting many of the benefits derived from techniques such as power gating.
FIG. 1 illustrates an electronic circuit including a number of logic stages interleaved with state-retention flip flops to facilitate power gating according to the prior art. More specifically, the electronic circuit 100 of FIG. 1 includes a number, “n” of logic stages 102-106, where each logic stage is separated from adjacent logic stages via state-retention flip flops 108a-108n as shown. Each state-retention flip flop 108 includes inputs for data (labeled “D”), normal operation mode and a low-power operation mode power supply rail voltages or “supply voltages” (Vdd and Vddc, where Vddc is a voltage lower than Vdd and Vddc is constantly applied to each of state-retention flip flops 108), a clock signal and a state-retention enable control signal as well as a data output (labeled “Q”). Electronic circuit 100 of FIG. 1 further includes a memory 112 for storage of an evaluation result of electronic circuit 100 or remote storage for system state of electronic circuit 100 as previously described.